1. Field of the Invention
In general, the present invention provides a system, method and program product for positioning I/O pads on a chip. Specifically, under the present invention, I/O pads are positioned on a wire bond chip based upon an automatic comparison of a group switching current to a predetermined maximum switching current.
2. Related Art
As microelectronic devices become more advanced and pervasive, better methods for developing chip designs are needed. For example, today peripheral wire bond chips are a popular technology. In general, a peripheral wire bond chip includes I/O pads or cells positioned in groups around a periphery thereof. Each I/O pad group generally includes a power pad for providing the necessary power to the group. The chip is typically mounted on a carrier, which is mounted on a card or the like through the use of a module balls or the like. Wire leads generally extend from the I/O pads to wire bond pads to provide electrical connectivity between the components. The positioning of the I/O pads on the chip is important to the overall functionality of the package because improper positioning could lead to various errors and malfunctions.
One typical characteristic that should be considered when positioning I/O pads is switching current. Specifically, each I/O pad group has a maximum switching current that can be sustained. However, it could be the case that a proposed arrangement of I/O pads would exceed this threshold. For example, assume that a particular chip is be able to sustain a total of 500 milliamperes for a single I/O pad group. Further assume that a group of nine I/O pads, each having a switching current of 60 milliamperes, is proposed for placement on the chip. In this case, the maximum switching current of 500 milliamperes would be exceeded because the proposed group would generate a total of 540 milliamperes. Accordingly, an alternative design must be achieved.
Currently, there is no existing technology that automatically checks switching currents for I/O pad groups. Specifically, today one or more testers must either manually make the necessary calculations for a proposed design, or actually implement the design and then test the resulting chip. Neither option is efficient or cost effective since a single chip could have a large quantity of pad groups. If a tester wished to examine switching current, he/she must make the necessary analysis for each pad group. Moreover, if the initial analysis required relocation of an I/O pad, the calculation must be repeated for the group receiving the I/O pad. Thus, the testing of a single chip can take several days.
In view of the foregoing, there exists a need for a system, method and program product for positioning I/O pads on a chip. Specifically, a need exists for a way to automatically determine whether group switching currents for proposed placements of I/O pad groups on a chip would exceed a predetermined maximum switching current. A further need exists for corrective action to be taken if any group switching current exceeds a maximum switching current. For example, a need exists for an I/O pad to be relocated to another I/O pad group such that a maximum switching current is not exceeded, or for an additional power pad to be inserted into the I/O pad group.